1. Field of the Invention
The invention relates to a method for fabrication a transistor, and more particularly, to a method for fabricating a MOS transistor with metal gate.
2. Description of the Prior Art
In the field of semiconductor fabrication, the use of polysilicon material is diverse. Having a strong resistance for heat, polysilicon materials are commonly used to fabricate gate electrodes for metal-oxide semiconductor transistors. The gate pattern fabricated by polysilicon materials is also used to form self-aligned source/drain regions as polysilicon readily blocks ions from entering the channel region.
However, devices fabricated by polysilicon still have many drawbacks. In contrast to most metal, polysilicon gates are fabricated by semiconductor materials having high resistance, which causes the polysilicon gate to work under a much lower rate than other metal gates. In order to compensate for slightly lowered rate of performance, a significant amount of silicides is applied during the fabrication of polysilicon processes, such that the performance of the device could be increased to an acceptable level.
Gate electrodes fabricated by polysilicon also causes a depletion effect. In most circumstances, the optimum doping concentration for polysilicon is between about 2×2020/cm3 and 3×1020/cm3. As most gate electrodes have a doping concentration of at least 5×1021/cm3, the limited doping concentration of polysilicon gates often results in a depletion region at the interface between the gate and the gate dielectric layer. This depletion region not only thickens the gate dielectric layer, but also lowers the capacitance of the gate, and ultimately reduces the driving ability of the device.
In order to solve this problem, double work function metal gates are used to replace conventional polysilicon to fabricate gate electrodes for MOS transistors. Conventional approach for fabricating metal gate transistors typically forms a NMOS transistor and a PMOS transistor on a substrate, in which each of the NMOS transistor and the PMOS transistor includes a dummy gate preferably composed of polysilicon. A dry etching and a wet etching process are conducted sequentially to empty the dummy gate of both NMOS and PMOS transistor, or the dummy gate of either one of the transistor, such as the dummy gate of the NMOS or PMOS transistor, and then a metal is filled into the emptied opening for forming a metal gate.
However, polysilicon loss often results as the dummy gate of the transistor is emptied. The polysilicon loss usually forms a recess at the tip of the dummy gate and the recess is unavoidably filled with metal as metal material is deposited into the emptied slot of the original dummy gate. The filled recess ultimately obstructs the removal of polysilicon material in the later process. Hence, how to resolve issue has become and important task in this field.